1. Technical Field
Embodiments described herein are related to the field of integrated circuit design, and more particularly, to detecting jitter on an integrated circuit.
2. Description of the Related Art
Digital logic designs generally include asynchronous logic blocks separated by clocked storage circuits. At the beginning of a clock cycle, the clocked storage circuits launch previously stored logic signals into an asynchronous logic block. The logic signals then propagate through the asynchronous logic block and are operated on in accordance with the logic function implemented in the asynchronous logic block. At the end of the clock cycle, the resultant logic signals are captured by another set of clocked storage elements.
In real integrated circuits, however, clock signals are not ideal. The period of a clock signal may vary from one cycle to another. This variation in a clock signal is commonly referred to as “jitter,” and may have numerous sources such as, variations in the clock generator (phase-locked loop), variation in power supply voltages, capacitive or inductive coupling into the clock signal from other nearby signals, and the like.
When designing digital logic circuits, digital logic designs allow for a certain amount of jitter (commonly referred to as “adding margin”) which limits the effect portion of a clock cycle in which logic work may be done. In some cases the added margin is estimated based on an analysis of the clock generation circuits, such as, e.g., phase-locked loops, characteristics of the semiconductor manufacturing process that will be used to fabricate the design, the clock distribution network, etc. After fabrication, the actual circuit may experience less jitter than estimated which would allow for a higher operation frequency. Alternatively, the actual circuit may be experience more jitter than estimated, which may prevent the circuit from achieving intended performance goals.